// **************************************************************
// COPYRIGHT(c)2016, Xidian University
// All rights reserved.
//
// IP LIB INDEX :  
// IP Name      :      
// File name    :  
// Module name  :  
// Full name    :  
// Time         : 2016 
// Author       : Wang-Weina 
// Email        : 327422289@qq.com
// Data         : 
// Version      : V 1.0 
// 
// Abstract     :
// Called by    :  
// 
// Modification history
// -----------------------------------------------------------------
// 21.6.11 将节点ID FIFO和优先级FIFO的写使能信号缩短为一个周期。lhb
// 
//
// *****************************************************************

// *******************
// TIMESCALE
// ******************* 
`timescale 1ns/1ps 

// *******************
// INFORMATION
// *******************

//*******************
//DEFINE(s)
//*******************
//`define UDLY 1    //Unit delay, for non-blocking assignments in sequential logic

//*******************
//DEFINE MODULE PORT
//*******************
module fp_info_ctrl(
    input wire clk,
    input wire rst_n,
    input wire mem_que_rdy, //调度模块初始化完成的信号
    input wire rx_ff_sop,
    input wire rx_ff_eop,
    input wire rx_ff_dval,
    input wire[4:0] rx_ff_mod,

    input wire fifo_full,

    input wire empty,
    input wire full,
    input insert_frame_flag, 
    input [7:0] insert_des_node_id,
    input [2:0] pri_insert_i,
    
    output reg des_node_wen,
    output reg[7:0] des_node_id,
    output reg[2:0] pri_insert_o,
    output reg[10:0] frame_length,
    output reg fifo_wren,

    output wire rx_rdy,  //
    output wire rd_rdy
    );

//*******************
//DEFINE LOCAL PARAMETER
//*******************
//parameter(s)

             
                                    

 

//*********************
//INNER SIGNAL DECLARATION
//*********************
//REGS
reg insert_frame_flag_d1;
//WIRES
wire insert_frame_flag_pos;
//*********************
//INSTANTCE MODULE
//*********************

//*********************
//MAIN CORE
//********************* 
always@(posedge clk or negedge rst_n)
  if(!rst_n)
    frame_length <= 11'd0;
  else if(rx_ff_sop)
    frame_length <= 11'd32;
  else if(rx_ff_dval && !rx_ff_eop)
    frame_length <= frame_length + 11'd32;
  else if(rx_ff_dval && rx_ff_eop)
    if(rx_ff_mod == 6'd0)
      frame_length <= frame_length + 11'd32;
    else 
      frame_length <= frame_length + {6'b0,rx_ff_mod};
  else 
    frame_length <= frame_length;
always@(posedge clk or negedge rst_n)
  if(!rst_n)
    fifo_wren <= 1'b0;
  else if(!fifo_full && rx_ff_eop)
    fifo_wren <= 1'b1;
  else 
    fifo_wren <= 1'b0;

always@(posedge clk or negedge rst_n)
  if(!rst_n)
    des_node_wen <= 1'b0;
  else if(insert_frame_flag_pos)
    des_node_wen <= 1'b1;
  else 
    des_node_wen <= 1'b0;
always@(posedge clk or negedge rst_n)
  if(!rst_n)
    des_node_id <= 10'h0;
  else if(insert_frame_flag_pos)
    des_node_id <= insert_des_node_id;
  else 
    des_node_id <= 10'b0;

always@(posedge clk or negedge rst_n)
  if(!rst_n)
    pri_insert_o <= 10'h0;
  else if(insert_frame_flag_pos)
    pri_insert_o <= pri_insert_i;
  else 
    pri_insert_o <= 10'b0;

assign rd_rdy = ~empty;
assign rx_rdy = ~full && mem_que_rdy;

//insert_frame_flag_pos
always @(posedge clk or negedge rst_n) begin
  if(!rst_n)begin
    insert_frame_flag_d1 <= 1'b0;
  end
  else begin
    insert_frame_flag_d1 <= insert_frame_flag_pos;
  end
end
assign insert_frame_flag_pos = insert_frame_flag && (!insert_frame_flag_d1);
//*********************
endmodule    // hookup byte controller block
    